Despite the packaging used for an integrated circuit or die, the die is generally bonded to an external substrate for electrical connections to other external devices or components. Similar substrates, such as printed circuit boards, have been used in the semiconductor packaging industry for various applications.
To maximize the efficient use of layers on these substrates, a single layer will typically comprise a ground plane for a first power loop and a power supply trace for a second power loop. These substrates may comprise many different power loops and may have various combinations of ground planes and power supply traces on multiple layers of the substrate. However, these typical configurations may incur problems, such as a high impedance on a power loop, as a result of how the ground plane and power supply trace may be configured on a single layer.
For example, in one layer, one typical configuration may include a ground plane for a first power loop that substantially surrounds two sides of the area where a die will be bonded to the substrate. An outer layer may comprise a ball grid array (BGA) that has power supply connections located on an outer corner of the substrate where a line between those connections the die area dissect the ground plane. Vias from these connections to the layer on which the ground plane is located may couple the power supply connections to a trace. In a typical configuration, the trace then bisects the ground plane and surrounds the die area on the same two sides that the ground plane does. Accordingly, the trace may have a “Y” configuration where the die area is situated within and between the upper branches of the “Y.” Return current in the ground plane may therefore be prevented from returning in a direct path because the trace may cut off the direct path. Rather, the return current may be diverted around the trace to return to vias that couple the die.
In these configurations, the diversion of the return current typically results in an increased impedance of the power loop. The increase in impedance may also become much more pronounced in higher frequencies. Further, this may result in increased power noise that reduces the fidelity of signals in the die. Accordingly, there is a need in the art for a substrate layout that reduces or obviates these disadvantages and a method for creating such a substrate layout.